| A Fully Integrated Genetic Variant Discovery SoC for Next-Generation Sequencing
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Yi-Chung Wu, Yen-Lung Chen, Chung-Hsuan Yang, Chao-Hsi Lee, Chao-Yang Yu, Nian-Shyang Chang, Ling-Chien Chen, Jia-Rong Chang, Chun-Pin Lin, Hung-Lieh Chen, Chi-Shi Chen, Jui-Hung Hung and Chia-Hsiang Yang; National Taiwan University |
| Chipyard – Integrated Design, Simulation, and Implementation of Custom RISC-V SoCs
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Alon Amid, Abraham Gonzalez, David Biancolin, Daniel Grubb, Sagar Karandikar, Harrison Liew, Albert Magyar, Howard Mao, Albert Ou, Nathan Pemberton, Paul Rigge, Colin Schmidt, John Wright, Jerry Zhao, Yakun Sophia Shao, Krste Asanovic and Borivoje Nikolic; UC Berkeley |
| A Mutual Information Accelerator for Autonomous Robot Exploration
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Peter Li, Sertac Karaman and Vivienne Sze; MIT |
| GANPU: A Versatile Many-Core Processor for Training GAN on Mobile Devices with Speculative Dual-Sparsity Exploitation
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Sanghoon Kang, Donghyeon Han, Juhyoung Lee, Dongseok Im, Sangyeob Kim, Soyeon Kim, Junha Ryu and Hoi-Jun Yoo; KAIST |
| Vortex: An Open Source Reconfigurable RISC-V GPGPU Accelerator for Architecture Research
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Fares Elsabbagh, Blaise Tine, Apurve Chawda, Will Gulian, Yaotian Feng, Da Eun Shim, Priyadarshini Roshan, Ethan Lyons, Lingjun Zhu, Sung Kyu Lim and Hyesoon Kim; Georgia Tech |
| Light-in-the-loop: Using a Photonics Co-processor for Scalable Training of Neural Networks
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Julien Launay, Iacopo Poli, Kilian Müller, Igor Carron, Laurent Daudet, Florent Krzakala and Sylvain Gigan; LightOn |
| ELearn: Edge Learning Processor with Bidirectional Speculation and Sparsity & Mixed-Precision Aware Dataflow Parallelism Reconfiguration
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Fengbin Tu, Weiwei Wu, Yang Wang, Hongjiang Chen, Feng Xiong, Man Shi, Ning Li, Jinyi Deng, Tianbao Chen, Leibo Liu, Shaojun Wei and Shouyi Yin; Tsinghua University |
| Fully Autonomous Mixed Signal SoC Design & Layout Generation Platform
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Tutu Ajayi, Yaswanth K Cherivirala, Kyumin Kwon, Sumanth Kamineni, Mehdi Saligane, Morteza Fayazi, Shourya Gupta, Chien-Hen Chen, Dennis Sylvester, David Blaauw, Ronald Dreslinski Jr, Benton Calhoun and David Wentzloff; University of Michigan |
| OmniCIM: A Sparsity-Aware Computing-in-Memory based Processor for Accelerating Arbitrary Quantized Neural Networks
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Jianxun Yang, Yuyao Kong, Yiqi Wang, Zhao Zhang, Jing Zhou, Zhuangzhi Liu, Yonggang Liu, Chenfu Guo, Te Hu, Congcong Li, Leibo Liu, Jun Yang, Shaojun Wei and Shouyi Yin; Tsinghua University |
| SAINT-S – 3D SRAM Stacking Solution Based on TSV Technology
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Kyoungsun Cho, Jinhong Park, Billy Koo, Sunkyoung Seo, Yoonjae Hwang, Sungcheol Park and Mijung Noh; Samsung |
| A 3.2Gbps/pin HBM2E PHY with Low Power I/O and Enhanced Training Scheme for 2.5D System-in-Package Solutions
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Sangyun Hwang, Kwanyeob Chae, Taekyung Yeo, Sangsoo Park, Won Lee, Shinyoung Lee, Soo-Min Lee, Kihwan Seong, Eunkyoung Ha, Eunsu Kim, Jihun Oh, Kyoung-Hoi Koo, Sanghune Park, Jongshin Shin; Samsung |